Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
In this role, you will be responsible for defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital and/or mixed-signal chips and/or IPs. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation SoCs. You will design, insert, and verify the DFT logic.You will prepare for post silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality, and enhancing yield.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Minimum qualifications:
1.10 years of Experience in DFT specification definition architecture and insertion.
2.Experience using electronic design automation (EDA) test tools (e.g., Spyglass, Tessent, etc.).
3.Experience with ASIC DFT synthesis, simulation, and verification flow.
4.Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, and debug of silicon issues, etc.).
Preferred qualifications:
1.Master's degree in Electrical Engineering.
2.Experience in IP integration (e.g., memories, test controllers, TAP, and MBIST).
3.Experience in SoC cycles, including silicon bring-up and silicon debug activities.
4.Experience in fault modeling.
Responsibilities
Develop DFT strategy and architecture, including hierarchical DFT/Memory Built-In Self Test (MBIST) and Automatic Test Pattern Generation (ATPG). Demonstrate ownership from DFT logic, Pre-silicon verification to Co-work with test engineers post silicon.
Insert DFT logic, including boundary scan, scan chains, DFT Compression, Logic Built-In Self Test (BIST), Test Access Point (TAP) controller, Clock Control block, and other DFT IP blocks.
Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic and connect to core and TAP interfaces.
Document DFT architecture and test sequences, including boot-up sequence associated with test pins.
Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high test quality.
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